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1 data sheet acquired from harris semiconductor schs218c features center frequency of 18mhz (typ) at v cc = 5v, minimum center frequency of 12mhz at v cc = 4.5v choice of two phase comparators - exclusive-or - edge-triggered jk flip-flop excellent vco frequency linearity vco-inhibit control for on/off keying and for low standby power consumption minimal frequency drift zero voltage offset due to op-amp buffer operating power-supply voltage range - vco section . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 6v - digital section . . . . . . . . . . . . . . . . . . . . . . . . 2v to 6v fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh applications fm modulation and demodulation frequency synthesis and multiplication frequency discrimination tone decoding data synchronization and conditioning voltage-to-frequency conversion motor-speed control related literature - an8823, cmos phase-locked-loop application using the cd74hc/hct7046a and cd74hc/hct7046a description the cd74hc7046a and cd74hct7046a high-speed silicon-gate cmos devices, speci?d in compliance with jedec standard no. 7a, are phase-locked-loop (pll) circuits that contain a linear voltage-controlled oscillator (vco), two-phase comparators (pc1, pc2), and a lock detector. a signal input and a comparator input are common to each comparator. the lock detector gives a high level at pin 1 (ld) when the pll is locked. the lock detector capacitor must be connected between pin 15 (c ld ) and pin 8 (gnd). for a frequency range of 100khz to 10mhz, the lock detector capacitor should be 1000pf to 10pf, respectively. the signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. a self-bias input circuit keeps small voltage signals within the linear region of the input ampli?rs. with a passive low-pass ?ter, the 7046a forms a second- order loop pll. the excellent vco linearity is achieved by the use of linear op-amp techniques. ordering information part number temp. range ( o c) package cd74hc7046ae -55 to 125 16 ld pdip cd74hc7046am -55 to 125 16 ld soic cd74hc7046amt -55 to 125 16 ld soic cd74hc7046am96 -55 to 125 16 ld soic cd74hct7046ae -55 to 125 16 ld pdip cd74hct7046am -55 to 125 16 ld soic cd74hct7046amt -55 to 125 16 ld soic cd74hct7046am96 -55 to 125 16 ld soic note: when ordering, use the entire part number. the suf? 96 denotes tape and reel. the suf? t denotes a small-quantity reel of 250. february 1998 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated 0.1 cd74hc7046a, cd74hct7046a phase-locked loop with vco and lock detector [ /title ( cd74 h c704 6 a, c d74 h ct70 4 6a) / sub- j ect ( phase- l ocked l oop
2 pinout cd74hc7046a, cd74hct7046a (pdip, soic) top view functional diagram 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 pc1 out comp in vco out inh c1 a gnd c1 b v cc sig in pc2 out r 2 r 1 dem out vco in c ld ld 10 4 vco out dem out 5 6 7 12 c1 a r 1 vco in inh 9 11 c1 b r 2 15 1 13 2 pc1 out c ld pc2 out ld 14 3 comp in sig in vco figure 1. logic diagram dem out r2 12 r1 r5 11 10 c1 r3 c2 pc2 out 13 p n gnd v cc 2 pc1 out down r d q q d cp r d q q d cp up v cc v cc inh 59 vco in vco - + vco out comp in - + sig in c1 b c1 a v ref r2 r1 674314 - + 1 15 150 ? 1.5k lock detector output lock detector capacitor c ld lock detector cd74hc7046a, cd74hct7046a
3 general description vco the vco requires one external capacitor c1 (between c1 a and c1 b ) and one external resistor r1 (between r1 and gnd) or two external resistors r1 and r2 (between r1 and gnd, and r2 and gnd). resistor r1 and capacitor c1 deter- mine the frequency range of the vco. resistor r2 enables the vco to have a frequency offset if required. see logic dia- gram, figure 1. the high input impedance of the vco simpli?s the design of low-pass ?ters by giving the designer a wide choice of resistor/capacitor ranges. in order not to load the low-pass ?ter, a demodulator output of the vco input voltage is pro- vided at pin 10 (dem out ). in contrast to conventional tech- niques where the dem out voltage is one threshold voltage lower than the vco input voltage, here the dem out voltage equals that of the vco input. if dem out is used, a load resistor (r s ) should be connected from dem out to gnd; if unused, dem out should be left open. the vco output (vco out ) can be connected directly to the comparator input (comp in ), or connected via a frequency-divider. the vco output signal has a speci?d duty factor of 50%. a low level at the inhibit input (inh) enables the vco, while a high level disables the vco to minimize standby power consumption. phase comparators the signal input (sig in ) can be directly coupled to the self- biasing ampli?r at pin 14, provided that the signal swing is between the standard hc family input logic levels, capaci- tive coupling is required for signals with smaller swings. phase comparator 1 (pc1) this is an exclusive-or network. the signal and comparator input frequencies (f i ) must have a 50% duty factor to obtain the maximum locking range. the transfer characteristic of pc1, assuming ripple (f r = 2f i ) is suppressed, is: v demout =(v cc / )( sigin - compin ) where v demout is the demodulator output at pin 10; v demout =v pc1out (via low-pass ?ter). the average output voltage from pc1, fed to the vco input via the low-pass ?ter and seen at the demodulator output at pin 10 (v demout ), is the resultant of the phase differences of signals (sig in ) and the comparator input (comp in )as shown in figure 2. the average of v dem is equal to 1/2 v cc when there is no signal or noise at sig in , and with this input the vco oscillates at the center frequency (f o ). typical wave- forms for the pc1 loop locked at f o shown in figure 3. the frequency capture range (2f c ) is de?ed as the fre- quency range of input signals on which the pll will lock if it was initially out-of-lock. the frequency lock range (2f l )is de?ed as the frequency range of input signals on which the loop will stay locked if it was initially in lock. the capture range is smaller or equal to the lock range. with pc1, the capture range depends on the low-pass ?ter characteristics and can be made as large as the lock range. this con?uration retains lock behavior even with very noisy input signals. typical of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the vco center frequency. phase comparator 2 (pc2) this is a positive edge-triggered phase and frequency detec- tor. when the pll is using this comparator, the loop is con- trolled by positive signal transitions and the duty factors of sigin and comp in are not important. pc2 comprises two d-type ?p-?ps, control-gating and a three-state output stage. the circuit functions as an up-down counter (figure 1) where sig in causes an up-count and comp in a down- count. the transfer function of pc2, assuming ripple (f r =f i ) is suppressed, is: v demout =(v cc /4 )( sign - compin ) where v demout is the demodulator output at pin 10; v demout =v pc2out (via low-pass ?ter). the average output voltage from pc2, fed to the vco via the low-pass ?ter and seen at the demodulator output at pin 10 (v demout ), is the resultant of the phase differences of sig in and comp in as shown in figure 4. typical waveforms for the pc2 loop locked at f o are shown in figure 5. when the frequencies of sig in and comp in are equal but the phase of sig in leads that of comp in , the p-type output driver at pc2 out is held ?n for a time corresponding to the phase differences ( demout ). when the phase of sig in lags that of comp in , the n-type driver is held ?n? when the frequency of sig in is higher than that of comp in , the p-type output driver is held ?n for most of the input sig- nal cycle time, and for the remainder of the cycle both n-type and p-type drivers are ?ff (three-state). if the sig in fre- pin descriptions pin no. symbol name and function 1 ld lock detector output (active high) 2 pc1 out phase comparator 1 output 3 comp in comparator input 4 vco out vco output 5 inh inhibit input 6c1 a capacitor c1 connection a 7c1 b capacitor c1 connection b 8 gnd ground (0v) 9 vco in vco input 10 dem out demodulator output 11 r 1 resistor r1 connection 12 r 2 resistor r2 connection 13 pc2 out phase comparator 2 output 14 sig in signal input 15 c ld lock detector capacitor input 16 v cc positive supply voltage cd74hc7046a, cd74hct7046a
4 quency is lower than the comp in frequency, then it is the n- type driver that is held ?n for most of the cycle. subse- quently, the voltage at the capacitor (c2) of the low-pass filter connected to pc2 out varies until the signal and comparator inputs are equal in both phase and frequency. at this stable point the voltage on c2 remains constant as the pc2 output is in three-state and the vco input at pin 9 is a high impedance. thus, for pc2, no phase difference exists between sig in and comp in over the full frequency range of the vco. moreover, the power dissipation due to the low-pass ?ter is reduced because both p-type and n-type drivers are ?ff for most of the signal input cycle. it should be noted that the pll lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass ?ter. with no signal present at sig in , the vco adjusts, via pc2, to its lowest frequency. lock detector theory of operation detection of a locked condition is accomplished by a nor gate and an envelope detector as shown in figure 6. when the pll is in lock, the output of the nor gate is high and the lock detector output (pin 1) is at a constant high level. as the loop tracks the signal on pin 14 (signal in), the nor gate outputs pulses whose widths represent the phase differ- ences between the vco and the input signal. the time between pulses will be approximately equal to the time con- stant of the vco center frequency. during the rise time of the pulse, the diode across the 1.5k ? resistor is forward biased and the time constant in the path that charges the lock detector capacitor is t = (150 ? x c ld ). during the fall time of the pulse the capacitor discharges through the 1.5k ? and the 150 ? resistors and the channel resistance of the n-device of the nor gate to ground (t = (1.5k ? + 150 ? + rn-channel) x c ld ). the waveform preset at the capacitor resembles a sawtooth as shown in figure 7. the lock detector capacitor value is determined by the vco center frequency. the typical range of capacitor for a frequency of 10mhz is about 10pf and for a frequency of 100khz is about 1000pf. the chart in figure 8 can be used to select the proper lock detector capacitor value. as long as the loop remains locked and tracking, the level of the sawtooth will not go below the switching thresh- old of the schmitt-trigger inverter. if the loop breaks lock, the width of the error pulse will be wide enough to allow the saw- tooth waveform to go below threshold and a level change at the output of the schmitt trigger will indicate a loss of lock, as shown in figure 9. the lock detector capacitor also acts to ?ter out small glitches that can occur when the loop is either seeking or losing lock. note: when using phase comparator 1, the detector will only indicate a lock condition on the fundamental frequency and not on the harmonics, which pc1 will also lock on. if a detec- tion of lock is needed over the harmonic locking range of pc1, then the lock detector output must be or-ed with the output of pc1. figure 2. phase comparator 1: average output voltage vs input phase difference: v demout = v pc1out = (v cc / ) ( sigin - com- pin ); demout = ( sigin - compin ) figure 3. typical waveforms for pll using phase comparator 1, loop locked at f o v cc v demout (av) 1/2 v cc 0 0 o 90 o demout 180 o sig in comp in vco out pc1 out vco in v cc gnd cd74hc7046a, cd74hct7046a
5 figure 4. phase comparator 2: average output voltage vs input phase difference: v demout = v pc2out = (v cc / ) ( sigin - com- pin ); demout = ( sigin - compin ) figure 5. typical waveforms for pll using phase comparator 2, loop locked at f o figure 6. cd74hc/hct7046a lock detector circuit figure 7. waveform present at lock detector capacitor when in lock v cc v demout (av) 1/2 v cc 0 -360 o 0 o demout 360 o sig in comp in vco out pc2 out vco in v cc gnd pcp out high impedance off - state up ff dn ff comp in sig in phase difference 7046 lock detector circuitry 1.5k ? 150 ? pin 1 lock detector output pin 15 c ld lock detector capacitor v cap v th lock detector output pin 1 c ld pin 15 lock detector capacitor 1.5k ? 150 ? cd74hc7046a, cd74hct7046a
6 figure 8. lock detector capacitor selection chart figure 9. waveform present at lock detector capacitor when unlocked 10m 1m 100k 10k 1k 100 10 10 100 1k 10k 100k 1m 10m 100m f, vco center frequency (hz) lock detector capacitor value (pf) v cap v th lock detector output pin 1 c ld pin 15 lock detector capacitor 1.5k ? 150 ? loss of lock cd74hc7046a, cd74hct7046a
7 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 1) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types vco section inh high level input voltage v ih - - 3 2.1 - - 2.1 - 2.1 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v inh low level input voltage v il - - 3 - - 0.9 - 0.9 - 0.9 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v vco out high level output voltage cmos loads v oh v ih or v il -0.02 3 2.9 - - 2.9 - 2.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v vco out high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v vco out low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v vco out low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v c1a, c1b low level output voltage (test purposes only) v ol v il or v ol 4 4.5 - - 0.40 - 0.47 - 0.54 v 5.2 6 - - 0.40 - 0.47 - 0.54 v cd74hc7046a, cd74hct7046a
8 inh vco in input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a r1 range (note 2) - - - 4.5 3 - - - - - - k ? r2 range (note 2) - - - 4.5 3 - - - - - - k ? c1 capacitance range ---3--no limit --- -pf 4.5 40 - - - - - pf 6-- --- -pf vco in operating voltage range - over the range specified for r1 for linearity see figure 8, and 35 - 38 (note 3) 3 1.1 - 1.9 - - - - v 4.5 1.1 - 3.2 - - - - v 6 1.1 - 4.6 - - - - v phase comparator section sig in , comp in dc coupled high-level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v sig in , comp in dc coupled low-level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v ld, pcn out high- level output voltage cmos loads v oh v il or v ih -0.02 2 1.9 - - 1.9 - 1.9 - v 4.5 4.4 - - 4.4 - 4.4 - v 6 5.9 - - 5.9 - 5.9 - v ld, pcn out high- level output voltage ttl loads v oh v il or v ih -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v ld, pcn out low- level output voltage cmos loads v ol v il or v ih 0.02 2 - - 0.1 - 0.1 - 0.1 v 4.5 - - 0.1 - 0.1 - 0.1 v 6 - - 0.1 - 0.1 - 0.1 v ld, pcn out low- level output voltage ttl loads v ol v il or v ih 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v sig in , comp in input leakage current i i v cc or gnd -2-- 3- 4- 5 a 3-- 7- 9- 11 a 4.5 - - 18 - 23 - 29 a 6-- 30 - 38 - 45 a pc2 out three-state off-state current i oz v il or v ih -6-- 0.5 - 5- 10 a sig in , comp in input resistance r i v i at self-bias operation point: ? v i = 0.5v, see figure 8 3 - 800 - - - - - k ? 4.5 - 250 - - - - - k ? 6 - 150 - - - - - k ? demodulator section resistor range r s at r s > 300k ? leakage current can influence v demout 3 10 - 300 - - - - k ? 4.5 10 - 300 - - - - k ? 6 10 - 300 - - - - k ? dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max cd74hc7046a, cd74hct7046a
9 offset voltage vco in to v dem v off v i = v vcoin = values taken over r s range see figure 15 3- 30 - - - - - mv 4.5 - 20 - - - - - mv 6- 10 - - - - - mv dynamic output resistance at dem out r o v demout =3-25----- ? 4.5 - 25 - - - - - ? 6 - 25 - - - - - ? quiescent device current i cc pins 3, 5 and 14 at v cc pin 9 at gnd, i i at pins 3 and 14 to be excluded 6 - - 8 - 80 - 160 a hct types vco section inh high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v inh low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v vco out high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v vco out high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v vco out low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v vco out low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v c1a, c1b low level output voltage (test purposes only) v ol v ih or v il 4 4.5 - - 0.40 - 0.47 - 0.54 v inh vco in input leakage current i i any voltage between v cc and gnd 5.5 - 0.1 - 1- 1 a r1 range (note 2) - - - 4.5 3 - - - - - - k ? r2 range (note 2) - - - 4.5 3 - - - - - - k ? c1 capacitance range - - - 4.5 40 - no limit --- -pf vco in operating voltage range - over the range specified for r1 for linearity see figure 8, and 35 - 38 (note 3) 4.5 1.1 - 3.2 - - - - v phase comparator section sig in , comp in dc coupled high-level input voltage v ih - - 4.5 to 5.5 3.15 - - 3.15 - 3.15 - v dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max v c c 2 v c c 2 cd74hc7046a, cd74hct7046a
10 sig in , comp in dc coupled low-level input voltage v il - - 4.5 to 5.5 - - 1.35 - 1.35 - 1.35 v ld, pcn out high- level output voltage cmos loads v oh v il or v ih - 4.5 4.4 - - 4.4 - 4.4 - v ld, pcn out high- level output voltage ttl loads v oh v il or v ih - 4.5 3.98 - - 3.84 - 3.7 - v ld, pcn out low- level output voltage cmos loads v ol v il or v ih - 4.5 - - 0.1 - 0.1 - 0.1 v ld, pcn out low- level output voltage ttl loads v ol v il or v ih - 4.5 - - 0.26 - 0.33 - 0.4 v sig in , comp in input leakage current i i any voltage between v cc and gnd - 5.5 - - 30 38 45 a pc2 out three-state off-state current i oz v il or v ih - 5.5 - - 0.5 5- - 10 a sig in , comp in input resistance r i v i at self-bias operation point: ? v, 0.5v, see figure 8 4.5 - 250 - - - - - k ? demodulator section resistor range r s at r s > 300k ? leakage current can influence v demout 4.5 10 - 300 - - - - k ? offset voltage vco in to v dem v off v i = v vcoin = values taken over r s range see figure 15 4.5 - 20 - - - - - mv dynamic output resistance at dem out r o v demout = 4.5 - 25 - - - - - ? quiescent device current i cc v cc or gnd - 5.5 - - 8 - 80 - 160 a additional quiescent device current per input pin: 1 unit load ? i cc (note 4) v cc -2.1 (exclud- ing pin 5) - 4.5 to 5.5 - 100 360 - 450 - 490 a notes: 2. the value for r1 and r2 in parallel should exceed 2.7k ? ; r1 and r2 values above 300k ? may contribute to frequency shift due to leakage currents. 3. the maximum operating voltage can be as high as v cc -0.9v, however, this may result in an increased offset voltage. 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max v c c 2 v c c 2 cd74hc7046a, cd74hct7046a
11 hct input loading table input unit loads inh 1 note: unit load is ? i cc limit speci?d in dc electrical table, e.g., 360 a max at 25 o c. switching speci?ations c l = 50pf, input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types phase comparator section propagation delay t plh , t phl sig in , comp in to pc 1out 2 - - 200 - 250 - 300 ns 4.5 - - 40 - 50 - 60 ns 6 - - 34 - 43 - 51 ns output transition time t thl , t tlh 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns output enable time, sig in , comp in to pc2 out t pzh , t pzl 2 - - 280 - 350 - 420 ns 4.5 - - 56 - 70 - 84 ns 6 - - 48 - 60 - 71 ns output disable time, sig in , comp in to pc2 out t phz , t plz 2 - - 325 - 405 - 490 ns 4.5 - - 65 - 81 - 98 ns 6 - - 55 - 69 - 83 ns ac coupled input sensitivity ( p- p ) at sig in or comp in v i(p-p) 3 - 11 - - - - - mv 4.5 - 15 - - - - - mv 6 - 33 - - - - - mv vco section frequency stability with temperature change ? f ? t r 1 = 100k ? , r 2 = 3 - - - typ 0.11 - - %/ o c 4.5 - - - - - %/ o c 6--- --%/ o c maximum frequency f max c 1 = 50pf r 1 = 3.5k ? r 2 = 3 - - - - - - - mhz 4.5 - 24 - - - - - mhz 6 - - - - - - - mhz c 1 = 0pf r 1 = 9.1k ? r 2 = 3 - - - - - - - mhz 4.5 - 38 - - - - - mhz 6 - - - - - - - mhz center frequency f o c 1 = 40pf r 1 = 3k ? r 2 = vco in =v cc /2 3 7 10 - - - - - mhz 4.5 12 17 - - - - - mhz 6 14 21 - - - - - mhz frequency linearity ? f vco r 1 = 100k ? r 2 = c 1 = 100pf 3-------% 4.5 - 0.4 - - - - - % 6-------% cd74hc7046a, cd74hct7046a
12 offset frequency r 2 = 220k ? c 1 = 1nf 3 - - - - - - - khz 4.5 - 400 - - - - - khz 6 - - - - - - - khz demodulator section v out vs f in r 1 = 100k ? r 2 = c 1 = 100pf r 5 = 10k ? r 3 = 100k ? c 2 = 100pf 3 - - - - - - - mv/khz 4.5 - 330 - - - - - mv/khz 6 - - - - - - - mv/khz hct types phase comparator section propagation delay t plh , t phl sig in , comp in to pc 1out 4.5 - - 45 - 56 - 68 ns output transition time t thl , t tlh 4.5 - - 15 - 19 - 22 ns output enable time, sig in , comp in to pc2 out t pzh , t pzl 4.5 - - 60 - 75 - 90 ns output disable time, sig in , comp in to pcz out t phz , t plz 4.5 - - 70 - 86 - 105 ns ac coupled input sensitivity ( p-p ) at sig in or comp in v i(p-p) 3 - 11 - - - - - mv 4.5 - 15 - - - - - mv 6 - 33 - - - - - mv vco section frequency stability with temperature change ? f ? t r 1 = 100k ? , r 2 = 4.5 - - - typ 0.11 - - %/ o c maximum frequency f max c 1 = 50pf r 1 = 3.5k ? r 2 = 4.5 - 24 - - - - - mhz c 1 = 0pf r 1 = 9.1k ? r 2 = 4.5 - 38 - - - - - mhz center frequency f o c 1 = 40pf r 1 = 3k ? r 2 = vco in =v cc /2 4.5 12 17 - - - - - mhz frequency linearity ? f vco r 1 = 100k ? r 2 = c 1 = 100pf 4.5 - 0.4 - - - - - % offset frequency r 2 = 220k ? c 1 = 1nf 4.5 - 400 - - - - - khz demodulator section v out vs f in r 1 = 100k ? r 2 = c 1 = 100pf r 5 = 10k ? r 3 = 100k ? c 2 = 100pf 4.5 - 330 - - - - - mv/khz switching speci?ations c l = 50pf, input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max cd74hc7046a, cd74hct7046a
13 test circuits and waveforms figure 10. hc transition times and propagation delay times, combination logic figure 11. hct transition times and propagation delay times, combination logic t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% typical performance curves figure 12. typical input resistance curve at sig in , comp in figure 13. hc7046a typical center frequency vs r1, c1 figure 14. hc7046a typical center frequency vs r1, c1 figure 15. hc7046a typical center frequency vs r1, c1 i i v i ? v i self-bias operating point 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) center frequency (hz) vco in = 0.5 v cc v cc = 4.5v r1 = 2.2k r1 = 22k r1 = 220k r1 = 2.2m r1 = 11m r2 = 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) center frequency (hz) vco in = 0.5 v cc v cc = 6.0v r1 = 3k r1 = 30k r1 = 330k r1 = 3m r1 = 15m r2 = 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) center frequency (hz) vco in = 0.5 v cc v cc = 3.0v r2 = r1 = 1.5k r1 = 15k r1 = 150k r1 = 1.5m r1 = 7.5m cd74hc7046a, cd74hct7046a
14 figure 16. hct7046a typical center frequency vs r1, c1 figure 17. hct7046a typical center frequency vs r1, c1 figure 18. hc7046a typical vco frequency vs vco in figure 19. hc7046a typical vco frequency vs vco in (r1 = 1.5m ? , c1 = 0.1 f) figure 20. hc7046a typical vco frequency vs vco in (r1 = 150k ? , c1 = 0.1 f) figure 21. hc7046a typical vco frequency vs vco in (r1 = 5.6k ? , c1 = 0.1 f) typical performance curves (continued) 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) center frequency (hz) vco in = 0.5 v cc v cc = 4.5v r1 = 2.2k r1 = 22k r1 = 220k r1 = 2.2m r1 = 11m r2 = 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) center frequency (hz) vco in = 0.5 v cc v cc = 5.5v r1 = 3k r1 = 30k r1 = 300k r1 = 3m r1 = 15m r2 = 140 120 100 80 60 40 20 01 2 3 456 vco in (v) vco frequency (khz) c1 = 50pf r1 = 1.5m v cc = 3v v cc = 4.5v v cc = 6v r2 = 90 70 60 50 40 30 20 10 01 2 3 4 5 6 vco in (v) vco frequency (hz) c1 = 0.1 f r1 = 1.5m v cc = 3v v cc = 4.5v v cc = 6v 80 r2 = c1 = 0.1 f r1 = 150k r2 = 800 600 500 400 300 200 100 01 2 3 4 5 6 vco in (v) vco frequency (hz) v cc = 3v v cc = 4.5v v cc = 6v 700 18 14 12 10 8 6 4 2 01 2 3 4 5 6 vco in (v) vco frequency (khz) c1 = 0.1 f r1 = 5.6k v cc = 3v v cc = 4.5v v cc = 6v 16 r2 = cd74hc7046a, cd74hct7046a
15 figure 22. hc7046a typical vco frequency vs vco in (r1 = 150k ? , c1 = 0.1 f) figure 23. hc7046a typical vco frequency vs vco in (r1 = 5.6k ? , c1 = 50pf) figure 24. hc7046a typical change in vco frequency vs ambient temperature as a function of r1 (v cc = 3v) figure 25. hc7046a typical change in vco frequency vs ambient temperature as a function of r1 typical performance curves (continued) 1400 1000 800 600 400 200 01 2 3 4 5 6 vco in (v) vco frequency (khz) v cc = 3v v cc = 4.5v v cc = 6v 1200 c1 = 50pf r1 = 150k r2 = 20 16 12 8 4 01 2 3 4 5 6 vco in (v) vco frequency (mhz) c1 = 50pf r1 = 5.6k v cc = 3v v cc = 4.5v v cc = 6v 24 r2 = r1 = 1.5m r1 = 150k r1 = 3k vco in = 0.5 v cc c1 = 50pf, v cc = 3v r2 = 24 16 12 8 4 0 -4 vco frequency change, ? f (%) 20 -75 -50 -25 0 25 50 75 ambient temperature, t a ( o c) 100 125 150 -8 -12 -16 r1 = 2.2m r1 = 220k r1 = 2.2k vco in = 0.5 v cc c1 = 50pf, v cc = 4.5v r2 = 16 12 8 4 0 vco frequency change, ? f (%) 20 -75 -50 -25 0 25 50 75 ambient temperature, t a ( o c) 100 125 150 -4 -8 -12 cd74hc7046a, cd74hct7046a
16 figure 26. hc7046a typical change in vco frequency vs ambient temperature as a function of r1 figure 27. hct7046a typical change in vco frequency vs ambient temperature as a function of r1 figure 28. hc7046a typical change in vco frequency vs ambient temperature as a function of r1 figure 29. hc7046a offset frequency vs r2, c1 figure 30. hc7046a offset frequency vs r2, c1 figure 31. hct7046a offset frequency vs r2, c1 typical performance curves (continued) r1 = 3m r1 = 300k r1 = 3k vco in = 0.5 v cc c1 = 50pf, v cc = 6.0v r2 = 16 12 8 4 0 vco frequency change, ? f (%) -75 -50 -25 0 25 50 75 ambient temperature, t a ( o c) 100 125 150 -4 -8 -12 r1 = 3m r1 = 300k r1 = 3k vco in = 0.5 v cc c1 = 50pf, v cc = 5.5v r2 = 16 12 8 4 0 vco frequency change, ? f (%) 20 -75 -50 -25 0 25 50 75 ambient temperature, t a ( o c) 100 125 150 -4 -8 -12 r1 = 2.2m r1 = 220k r1 = 2.2k vco in = 0.5 v cc c1 = 50pf, v cc = 4.5v r2 = 16 12 8 4 0 vco frequency change, ? f (%) 20 -75 -50 -25 0 25 50 75 ambient temperature, t a ( o c) 100 125 150 -4 -8 -12 r2 = 2.2k r2 = 22k r2 = 220k vco in = 0.5 v cc v cc = 4.5v 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 offset frequency (hz) r2 = 2.2m r2 = 11m vco in = gnd v cc = 3v 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 offset frequency (hz) r2 = 1.5k r2 = 15k r2 = 150k r2 = 1.5m r2 = 7.5m vco in = gnd v cc = 4.5v 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 offset frequency (hz) r2 = 2.2k r2 = 22k r2 = 220k r2 = 2.2m r2 = 11m cd74hc7046a, cd74hct7046a
17 figure 32. hc7046a and hct7046a offset frequency vs r2, c1 figure 33. hc7046a f min /f max vs r2/r1 figure 34. hct7046a f max /f min vs r2/r1 figure 35. definition of vco frequency linearity figure 36. hc7046a vco linearity vs r1 figure 37. hc7046a vco linearity vs r1 typical performance curves (continued) 110 10 2 10 3 10 4 10 5 10 6 capacitance, c1 (pf) 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 offset frequency (hz) r2 = 3k r2 = 30k r2 = 300k r2 = 3m r2 = 15m vco in = gnd hc - v cc = 6v hct - v cc = 5.5v vco in = v cc - 0.9v for f max vco in = 0v for f min v cc = 3v, 4.5v, 6v 10 2 10 f max /f min 1 10 -2 10 -1 1 r2/r1 10 2 10 vco in = v cc - 0.9v for f max vco in = 0v for f min v cc = 4.5v to 5.5v 10 2 10 f max /f min 1 10 -2 10 -1 1 r2/r1 10 2 10 f f 2 f 0 f 0 f 1 ? v 1/2v cc v vcoin min max ? v ? v = 0.5v over the v cc range : for vco linearity f o = f 1 + f 2 2 linearity = f o - f o f o x 100% 1k 10k 100k 1m 10m r1 (ohms) 8 6 4 2 0 -2 -4 -6 -8 linearity (%) vco in = 2.25v 1v c1 = 50pf v cc = 4.5v r2 = vco in = 2.25v 0.45v 1k 10k 100k 1m 10m r1 (ohms) 8 6 4 2 0 -2 -4 -6 -8 linearity (%) vco in = 1.50v 0.4v c1 = 50pf v cc = 3v r2 = vco in = 1.50v 0.3v cd74hc7046a, cd74hct7046a
18 figure 38. hc7046a vco linearity vs r1 figure 39. hct7046a vco linearity vs r1 figure 40. hc7046a demodulator power dissipation vs rs (typ) figure 41. hct7046a demodulator power dissipation vs rs (typ) (v cc = 3v, 4.5v, 6v) figure 42. hc7046a vco power dissipation vs r1 (c1 = 50pf, 1 f) figure 43. hct7046a vco power dissipation vs r2 (c1 = 50pf, 1 f) typical performance curves (continued) 1k 10k 100k 1m 10m r1 (ohms) 8 6 4 2 0 -2 -4 -6 -8 linearity (%) vco in = 3v 1.5v c1 = 50pf v cc = 6v r2 = vco in = 3v 0.6v 1k 10k 100k 1m 10m r1 (ohms) 8 6 4 2 0 -2 -4 -6 -8 linearity (%) v cc = 5.5v, c1 = 50pf r2 = open v cc = 4.5v, vco in = 2.75v 1.3v vco in = 2.25v 1.0v v cc = 5.5v, v cc = 4.5v, vco in = 2.75v 0.55v vco in = 2.25v 0.45v vco in = 0.5 v cc 1k 10k 100k 1m rs (ohms) 10 4 10 3 10 2 10 1 v cc = 3v v cc = 4.5v v cc = 6v demodulator power dissipation, p d ( w) vco in = 0.5 v cc 1k 10k 100k 1m rs (ohms) 10 4 10 3 10 2 10 1 v cc = 3v v cc = 4.5v v cc = 6v r1 = r2 = open demodulator power dissipation, p d ( w) vco in = 0.5v cc 1k 10k 100k 1m r1 (ohms) 10 6 10 5 10 4 10 3 10 2 r2 = rs = open c l = 50pf v cc = 6v c1 = 50pf v cc = 3v c1 = 1 f vco power dissipation, p d ( w) v cc = 6v c1 = 1 f v cc = 3v c1 = 50pf v cc = 4.5v c1 = 1 f v cc = 4.5v c1 = 50pf vco in = 0v (at f min ) 1k 10k 100k 1m r2 (ohms) 10 6 10 5 10 4 10 3 10 2 r1 = rs = c l = 50pf v cc = 6v c1 = 50pf v cc = 4.5v c1 = 1 f vco power dissipation, p d ( w) v cc = 4.5v c1 = 50pf v cc = 6v c1 = 1 f cd74hc7046a, cd74hct7046a
19 figure 44. hct7046a vco power dissipation vs r1 (c1 = 50pf, 1 f) figure 45. hc7046a vco power dissipation vs r2 (c1 = 50pf, 1 f) typical performance curves (continued) vco in = 0.5v 1k 10k 100k 1m r1 (ohms) 10 6 10 5 10 4 10 3 10 2 r2 = rs = v cc = 5.5v c1 = 50pf v cc = 5.5v c1 = 1 f vco power dissipation, p d ( w) v cc = 4.5v c1 = 50pf v cc = 4.5v c1 = 1 f vco in = 0v (at f min ) 1k 10k 100k 1m r2 (ohms) 10 6 10 5 10 4 10 3 10 2 r1 = rs = c l = 50pf v cc = 6v c1 = 50pf v cc = 3v c1 = 1 f vco power dissipation, p d ( w) v cc = 4.5v c1 = 1 f v cc = 4.5v c1 = 50pf v cc = 6v c1 = 1 f v cc = 3v c1 = 50pf cd74hc7046a, cd74hct7046a
20 application information this information is a guide for the approximation of values of external components to be used with the cd74hc7046a and cd74hct7046a in a phase-lock-loop system. references should be made to figures 13 through 23 and figures 36 through 41 as indicated in the table. values of the selected components should be within the fol- lowing ranges: hc/hct7046a c pd chip section hc hct unit comparator 1 48 50 pf comparator 2 39 48 pf vco 61 53 pf r1 > 3k ? ; r2 > 3k ? ; r1 || r2 parallel value > 2.7k ?; c1 greater than 40pf subject phase comparator design considerations vco frequency without extra offset (r2 = ) pc1 or pc2 vco frequency characteristic the characteristics of the vco operation are shown in figures 13 - 23. pc1 selection of r1 and c1 given f o , determine the values of r1 and c1 using figures 13 - 17. pc2 given f max calculate f o as f max /2 and determine the values of r1 and c1 using figures 13 - 17. to obtain 2f l : 2f l where 0.9v < vco in < v cc - 0.9v is the range of ? vco in vco frequency with extra offset (r2 > 3k ? ) pc1 or pc2 vco frequency characteristic the characteristics of the vco operation are shown in figures 29 - 32. pc1 or pc2 selection of r1, r2 and c1 given f o and f l , offset frequency, f min , may be calculated from f min f o - 1.6 f l . obtain the values of c1 and r2 by using figures 29 - 32. calculate the values of r1 from figures 33 - 34. figure 46. frequency characteristic of vco operating without offset: f o = center frequency: 2f l = frequency lock range f max f vco f o f min min 1/2 v cc v vcoin max 2f l 2( ? vco in ) r1c1 figure 47. frequency characteristic of vco operating with offset: f o = center frequency: 2f l = frequency lock range f max f vco f o f min min 1/2 v cc v vcoin max 2f l cd74hc7046a, cd74hct7046a
21 lock detector circuit the lock detector feature is very useful in data synchroniza- tion, motor speed control, and demodulation. by adjusting the value of the lock detector capacitor so that the lock out- put will change slightly before actually losing lock, the designer can create an ?arly warning indication allowing corrective measures to be implemented. the reverse is also true, especially with motor speed controls, generators, and clutches that must be set up before actual lock occurs or dis- connected during loss of lock. when using phase comparator 1, the detector will only indi- cate a lock condition on the fundamental frequency and not on the harmonics, which pc1 will lock on. pll conditions with no signal at the sig in input pc1 vco adjusts to f o with demout = 90 o and v vcoin = 1/2 v cc (see figure 2) pc2 vco adjusts to f min with demout = -360 o and v vcoin = 0v (see figure 4) pll frequency capture range pc1 or pc2 loop filter component selection pll locks on harmonics at center frequency pc1 yes pc2 no noise rejection at signal input pc1 high pc2 low ac ripple content when pll is locked pc1 f r = 2f i , large ripple content at demout = 90 o pc2 f r = f i , small ripple content at demout = 0 o subject phase comparator design considerations a small capture range (2f c ) is obtained if > 2f c (1/ ) (2 f l / 1 .) 1/2 figure 48. simple loop filter for pll without offset (a) 1 = r3 x c2 (b) amplitude characteristic (c) pole-zero diagram r3 c2 input output |f (j ) | -1/ figure 49. simple loop filter for pll with offset (a) 2 = r4 x c2; (b) amplitude characteristic (c) pole-zero diagram |f (j ) | -1/ 2 r3 c2 input output 3 = (r3 + r4) x c2 -1/ 3 m 1/ 3 1/ 2 r4 m = r4 r3 + r4
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) cd74hc7046ae active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc7046aee4 active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc7046am active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc7046am96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc7046am96e4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc7046ame4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc7046amt active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc7046amte4 active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct7046ae active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hct7046aee4 active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hct7046am active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct7046am96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT7046AM96E4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct7046ame4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct7046amt active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct7046amte4 active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. package option addendum www.ti.com 17-oct-2005 addendum-page 1
important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 17-oct-2005 addendum-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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